UNIFY=DUAL_COUNTER, CKSEL=INPUT_0_RISING_EDGES, CLKMODE=SYSTEM_CLOCK_MODE
SCT configuration register
| UNIFY | SCT operation 0 (DUAL_COUNTER): The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. 1 (UNIFIED_COUNTER): The SCT operates as a unified 32-bit counter. |
| CLKMODE | SCT clock mode 0 (SYSTEM_CLOCK_MODE): System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. 1 (SAMPLED_SYSTEM_CLOCK_MODE): Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. 2 (SCT_INPUT_CLOCK_MODE): SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. 3 (ASYNCHRONOUS_MODE): Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. |
| CKSEL | SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. 0 (INPUT_0_RISING_EDGES): Rising edges on input 0. 1 (INPUT_0_FALLING_EDGE): Falling edges on input 0. 2 (INPUT_1_RISING_EDGES): Rising edges on input 1. 3 (INPUT_1_FALLING_EDGE): Falling edges on input 1. 4 (INPUT_2_RISING_EDGES): Rising edges on input 2. 5 (INPUT_2_FALLING_EDGE): Falling edges on input 2. 6 (INPUT_3_RISING_EDGES): Rising edges on input 3. 7 (INPUT_3_FALLING_EDGE): Falling edges on input 3. |
| NORELAOD_L | A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. |
| NORELOAD_H | A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. |
| INSYNC | Synchronization for input N (bit 9 = input 0, bit 10 = input 1, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. |
| AUTOLIMIT_L | A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. |
| AUTOLIMIT_H | A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. |